The transition from aluminum to copper in integrated circuit (IC) fabrication required a change in process “architecture” (to damascene and dual-damascene) as well as a whole new set of process technologies. One process step used in producing copper damascene circuits is the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (electrofill). The seed layer carries the electrical plating current from the edge region of the wafer (where electrical contact is made) to all trench and via structures located across the wafer surface. The seed film is typically a thin conductive copper layer. It is separated from the insulating silicon dioxide or other dielectric by a barrier layer. The use of thin seed layers having dual barrier-seed function (e.g. alloys of copper, or other metals, such as ruthenium and tantalum), has also been investigated.
As semiconductor industry advances, technology nodes are moving towards very thin and resistive seed regime for electrochemical fill. It becomes a very challenging problem to achieve uniform initial plating across the wafer with such resistive seed layers. To effectively plate a large surface area, the plating tool makes electrical contact to the conductive seed only in the edge region of the wafer substrate. There is no direct contact made to the central region of the substrate. Hence, for highly resistive seed layers, the potential at the edge of the layer is significantly greater than at the central region of the layer. Without appropriate means of resistance and voltage compensation, this large edge-to-center voltage drop could lead to an extremely non-uniform plating thickness distribution, primarily characterized by thicker plating at the wafer edge. This effect is known as terminal effect.
The non-uniform plating thickness will be even more pronounced as the industry transitions from 300 mm wafer to 450 mm wafer.